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   <div id="projectname">CMSIS-Core (Cortex-A)
   &#160;<span id="projectnumber">Version 1.2.1</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<div class="header">
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<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">ACTLR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a></div></div>  </div>
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<div class="contents">

<p>Bit field declaration for ACTLR layout.  
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ac953059faa3a1139f8787d87f58a875d"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a50827448ef15f15f922e10a1c609f5d3"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781">FW</a>:1</td></tr>
<tr class="memdesc:a50827448ef15f15f922e10a1c609f5d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0 Cache and TLB maintenance broadcast  <a href="#a50827448ef15f15f922e10a1c609f5d3">More...</a><br/></td></tr>
<tr class="separator:a50827448ef15f15f922e10a1c609f5d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4756b5b7479e4e5f5c27c841f99b50e8"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">SMP</a>:1</td></tr>
<tr class="memdesc:a4756b5b7479e4e5f5c27c841f99b50e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 6 Enables coherent requests to the processor  <a href="#a4756b5b7479e4e5f5c27c841f99b50e8">More...</a><br/></td></tr>
<tr class="separator:a4756b5b7479e4e5f5c27c841f99b50e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1019cd812c2931a4e7eb82996127bebd"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91">EXCL</a>:1</td></tr>
<tr class="memdesc:a1019cd812c2931a4e7eb82996127bebd"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 7 Exclusive L1/L2 cache control  <a href="#a1019cd812c2931a4e7eb82996127bebd">More...</a><br/></td></tr>
<tr class="separator:a1019cd812c2931a4e7eb82996127bebd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaffa24a5ff6bf987d4ad0d73cafd014b"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8">DODMBS</a>:1</td></tr>
<tr class="memdesc:aaffa24a5ff6bf987d4ad0d73cafd014b"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 10 Disable optimized data memory barrier behavior  <a href="#aaffa24a5ff6bf987d4ad0d73cafd014b">More...</a><br/></td></tr>
<tr class="separator:aaffa24a5ff6bf987d4ad0d73cafd014b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9689f28161ce8516e8a74f1fb7cf1007"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#ad8faaa57629f258c6eba678ba8efc9da">DWBST</a>:1</td></tr>
<tr class="memdesc:a9689f28161ce8516e8a74f1fb7cf1007"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 11 AXI data write bursts to Normal memory  <a href="#a9689f28161ce8516e8a74f1fb7cf1007">More...</a><br/></td></tr>
<tr class="separator:a9689f28161ce8516e8a74f1fb7cf1007"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1873f12ba4059c242c4d73c3c669532e"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a7921e6e73e0841402a5519f09e6e2ef3">RADIS</a>:1</td></tr>
<tr class="memdesc:a1873f12ba4059c242c4d73c3c669532e"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 12 L1 Data Cache read-allocate mode disable  <a href="#a1873f12ba4059c242c4d73c3c669532e">More...</a><br/></td></tr>
<tr class="separator:a1873f12ba4059c242c4d73c3c669532e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a473b5ba32637965efc11c81809e2b3e2"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a5464ac7b26943d2cb868c154b0b1375c">L1PCTL</a>:2</td></tr>
<tr class="memdesc:a473b5ba32637965efc11c81809e2b3e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:13..14 L1 Data prefetch control  <a href="#a473b5ba32637965efc11c81809e2b3e2">More...</a><br/></td></tr>
<tr class="separator:a473b5ba32637965efc11c81809e2b3e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab446bfb09f286a0fabd62c9204bda75e"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#ac8ac735e3001442e581ae37e773b5929">BP</a>:2</td></tr>
<tr class="memdesc:ab446bfb09f286a0fabd62c9204bda75e"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:16..15 Branch prediction policy  <a href="#ab446bfb09f286a0fabd62c9204bda75e">More...</a><br/></td></tr>
<tr class="separator:ab446bfb09f286a0fabd62c9204bda75e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a364f4cc4a6eef60fb3476fd8fe6ff748"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a91288f7320d267d76b4aad4adcf8cda3">RSDIS</a>:1</td></tr>
<tr class="memdesc:a364f4cc4a6eef60fb3476fd8fe6ff748"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 17 Disable return stack operation  <a href="#a364f4cc4a6eef60fb3476fd8fe6ff748">More...</a><br/></td></tr>
<tr class="separator:a364f4cc4a6eef60fb3476fd8fe6ff748"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab74d59bda944b237ad561ab6b8d9e452"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#ad1a121373ae8df19f6d11bde3b3ba9c9">BTDIS</a>:1</td></tr>
<tr class="memdesc:ab74d59bda944b237ad561ab6b8d9e452"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 18 Disable indirect Branch Target Address Cache (BTAC)  <a href="#ab74d59bda944b237ad561ab6b8d9e452">More...</a><br/></td></tr>
<tr class="separator:ab74d59bda944b237ad561ab6b8d9e452"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa4ff9dd0a9fba2327631b183b09203cb"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a19e5f8f1a2ad8634619399b4eb50a449">DBDI</a>:1</td></tr>
<tr class="memdesc:aa4ff9dd0a9fba2327631b183b09203cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 28 Disable branch dual issue  <a href="#aa4ff9dd0a9fba2327631b183b09203cb">More...</a><br/></td></tr>
<tr class="separator:aa4ff9dd0a9fba2327631b183b09203cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac953059faa3a1139f8787d87f58a875d"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#ac953059faa3a1139f8787d87f58a875d">b</a></td></tr>
<tr class="memdesc:ac953059faa3a1139f8787d87f58a875d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access on Cortex-A5.  <a href="#ac953059faa3a1139f8787d87f58a875d">More...</a><br/></td></tr>
<tr class="separator:ac953059faa3a1139f8787d87f58a875d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a94d750b9b337ce140b04d6e30e7a2ca2"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:ae2aae6b9f3b12894f4a615c095a6a889"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">SMP</a>:1</td></tr>
<tr class="memdesc:ae2aae6b9f3b12894f4a615c095a6a889"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 6 Enables coherent requests to the processor  <a href="#ae2aae6b9f3b12894f4a615c095a6a889">More...</a><br/></td></tr>
<tr class="separator:ae2aae6b9f3b12894f4a615c095a6a889"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a523e7c03812bc6962252e3a22022aa4c"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8">DODMBS</a>:1</td></tr>
<tr class="memdesc:a523e7c03812bc6962252e3a22022aa4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 10 Disable optimized data memory barrier behavior  <a href="#a523e7c03812bc6962252e3a22022aa4c">More...</a><br/></td></tr>
<tr class="separator:a523e7c03812bc6962252e3a22022aa4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add3dfd4a681eb6b3f88229f0bce6042f"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a947f73d64ebde186b9416fd6dc66bc26">L2RADIS</a>:1</td></tr>
<tr class="memdesc:add3dfd4a681eb6b3f88229f0bce6042f"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 11 L2 Data Cache read-allocate mode disable  <a href="#add3dfd4a681eb6b3f88229f0bce6042f">More...</a><br/></td></tr>
<tr class="separator:add3dfd4a681eb6b3f88229f0bce6042f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0cb4299988efa4fc3364898111f834ff"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a3800bdd7abfab1a51dcfa7069e245d65">L1RADIS</a>:1</td></tr>
<tr class="memdesc:a0cb4299988efa4fc3364898111f834ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 12 L1 Data Cache read-allocate mode disable  <a href="#a0cb4299988efa4fc3364898111f834ff">More...</a><br/></td></tr>
<tr class="separator:a0cb4299988efa4fc3364898111f834ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aec089f449dbf249eb34dba39c7198805"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a5464ac7b26943d2cb868c154b0b1375c">L1PCTL</a>:2</td></tr>
<tr class="memdesc:aec089f449dbf249eb34dba39c7198805"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:13..14 L1 Data prefetch control  <a href="#aec089f449dbf249eb34dba39c7198805">More...</a><br/></td></tr>
<tr class="separator:aec089f449dbf249eb34dba39c7198805"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9254469bb22c156ff411e35ef0751121"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a4fe04e95b26e089642bee6952f223f82">DDVM</a>:1</td></tr>
<tr class="memdesc:a9254469bb22c156ff411e35ef0751121"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 15 Disable Distributed Virtual Memory (DVM) transactions  <a href="#a9254469bb22c156ff411e35ef0751121">More...</a><br/></td></tr>
<tr class="separator:a9254469bb22c156ff411e35ef0751121"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3be842fda0aa2525ce4e9a151396403"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#ab938c32e10162d06ba6b02400e955e01">DDI</a>:1</td></tr>
<tr class="memdesc:ad3be842fda0aa2525ce4e9a151396403"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 28 Disable dual issue  <a href="#ad3be842fda0aa2525ce4e9a151396403">More...</a><br/></td></tr>
<tr class="separator:ad3be842fda0aa2525ce4e9a151396403"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a94d750b9b337ce140b04d6e30e7a2ca2"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#a94d750b9b337ce140b04d6e30e7a2ca2">b</a></td></tr>
<tr class="memdesc:a94d750b9b337ce140b04d6e30e7a2ca2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access on Cortex-A7.  <a href="#a94d750b9b337ce140b04d6e30e7a2ca2">More...</a><br/></td></tr>
<tr class="separator:a94d750b9b337ce140b04d6e30e7a2ca2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5044f19ce5ae1f73dda07f7187e70923"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a5a318416ffc6404c2ba937554c5b869a"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781">FW</a>:1</td></tr>
<tr class="memdesc:a5a318416ffc6404c2ba937554c5b869a"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0 Cache and TLB maintenance broadcast  <a href="#a5a318416ffc6404c2ba937554c5b869a">More...</a><br/></td></tr>
<tr class="separator:a5a318416ffc6404c2ba937554c5b869a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a697e277c2fd70cfbf4454224371f0a1f"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#aacb87aa6bf093e1ee956342e0cb5903e">L1PE</a>:1</td></tr>
<tr class="memdesc:a697e277c2fd70cfbf4454224371f0a1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 2 Dside prefetch  <a href="#a697e277c2fd70cfbf4454224371f0a1f">More...</a><br/></td></tr>
<tr class="separator:a697e277c2fd70cfbf4454224371f0a1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acadb7b00e0fa53eb081040f50a97b6be"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a67e005f7741b6d46cf95d9c477efef36">WFLZM</a>:1</td></tr>
<tr class="memdesc:acadb7b00e0fa53eb081040f50a97b6be"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 3 Cache and TLB maintenance broadcast  <a href="#acadb7b00e0fa53eb081040f50a97b6be">More...</a><br/></td></tr>
<tr class="separator:acadb7b00e0fa53eb081040f50a97b6be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6972b588e58acb9aada88fd820eb883d"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">SMP</a>:1</td></tr>
<tr class="memdesc:a6972b588e58acb9aada88fd820eb883d"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 6 Enables coherent requests to the processor  <a href="#a6972b588e58acb9aada88fd820eb883d">More...</a><br/></td></tr>
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<tr class="memitem:a2391993a4a3b7e476627de84650571a1"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91">EXCL</a>:1</td></tr>
<tr class="memdesc:a2391993a4a3b7e476627de84650571a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 7 Exclusive L1/L2 cache control  <a href="#a2391993a4a3b7e476627de84650571a1">More...</a><br/></td></tr>
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<tr class="memitem:ada7513bf16860a33ac99cce7f4eb2394"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a3f235030777fe4e20477063df416b515">AOW</a>:1</td></tr>
<tr class="memdesc:ada7513bf16860a33ac99cce7f4eb2394"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 8 Enable allocation in one cache way only  <a href="#ada7513bf16860a33ac99cce7f4eb2394">More...</a><br/></td></tr>
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<tr class="memitem:aba098bbde24ff39c967d472b7c0c9f8a"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a6e8f053d01fb236cc7d002b04d93a19c">PARITY</a>:1</td></tr>
<tr class="memdesc:aba098bbde24ff39c967d472b7c0c9f8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 9 Support for parity checking, if implemented  <a href="#aba098bbde24ff39c967d472b7c0c9f8a">More...</a><br/></td></tr>
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<tr class="memitem:a5044f19ce5ae1f73dda07f7187e70923"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#a5044f19ce5ae1f73dda07f7187e70923">b</a></td></tr>
<tr class="memdesc:a5044f19ce5ae1f73dda07f7187e70923"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access on Cortex-A9.  <a href="#a5044f19ce5ae1f73dda07f7187e70923">More...</a><br/></td></tr>
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<tr class="memitem:ac65c09d839f8a78340c3b81d3bc90e4d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#ac65c09d839f8a78340c3b81d3bc90e4d">w</a></td></tr>
<tr class="memdesc:ac65c09d839f8a78340c3b81d3bc90e4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type used for word access.  <a href="#ac65c09d839f8a78340c3b81d3bc90e4d">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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